In the fabrication of integrated circuits, as the sizes of semiconductor devices, such as state-of-the-art Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), are scaled down, performance issues regarding the current driving capabilities of these devices exist. Since the current driving capability is a function of both source resistance and gate oxide thickness, better performance in these devices is achievable through thinner gate oxide and spacer layers. However, it has been observed that as the gate oxide is made thinner, gate-induced drain leakage (GIDL) currents degrade the performance of these devices as the GIDL currents become a larger percentage of the total sub-threshold leakage current. The GIDL currents are due to electrons from the valence band tunneling to the conduction band as a result of excessive band bending in the gate/drain overlap region. As these semiconductor devices scale down, the layer thickness of the gate oxide must continue to be reduced in order to provide for suitable gate control over the sub-threshold region. Also, doping density in the channel and source/drain regions must increase to improve punch through characteristics and increase drives. Unfortunately, it has been observed that by increasing the doping density in the channel and source/drain regions, the surface electric field also increases, resulting in more band bending and hence, even more GIDL current. Thus, difficulties exist in providing a scaled down semiconductor device having a suitable balance between high current driving capability and low GIDL current.
One approach for reducing GIDL currents involves symmetrical oxidation in order to provide a thick gate oxide only in the regions of the gate-source and gate-drain overlap. The thick gate oxide in the gate-drain region reduces GIDL. However, having a thick gate oxide in the gate-source region increases source resistance, which in turn, reduces the current driving capability of the device.
Another approach is disclosed by U.S. Pat. No. 5,684,317 to Hwang, who teaches forming a thick oxide layer only in the gate-drain region in order to reduce GIDL current without increasing source resistance. The material thickness of the oxide layer in the gate-drain region is increased by implanting an oxidation accelerating material, such as chlorine or fluorine, to physically grow a thicker gate oxide layer in that region. Due to the presence of the oxidation accelerating material, the oxide layer in the gate-drain region grows faster than the remaining portions on the substrate. However, having an increased material thickness of the oxide layer in the gate-drain region hampers current drives of the transistor and also cause increased stress in the active area near the overlap region due to volume expansion.
Accordingly, a need exists for a scaled-down semiconductor device having a thinner gate oxide with improved electrical performance which overcomes the disadvantages of the prior art. The semiconductor device and its method of fabrication should be cost effective and manufacturable, should be easily integrated into an existing process flow, and should not significantly increase the cycle time of the process flow.